Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), non-volatile, floating gate NOR/NAND flash memory, and dynamic random access memory (DRAM).
Flash memories may use floating gate technology or trapping technology. Floating gate cells include source and drain regions that may be laterally spaced apart to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. The floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. The non-volatile memory function for the floating gate technology is created by the absence or presence of charge stored on the isolated floating gate. The floating gate cell may be a single level cell (SLC) or a multiple level cell (MLC).
The trapping technology functions as a non-volatile memory and can be implemented in a silicon-oxide-nitride-oxide-silicon (SONOS) architecture as illustrated in FIG. 1. The nitride trap layer can capture and store electrons or holes in order to act as a non-volatile memory. The cell may be an SLC or an MLC.
Each cell's threshold voltage (Vth) determines the data that is stored in the cell. For example, in a single bit per cell, a Vth of 0.5V might indicate a programmed cell while a Vth of −0.5V might indicate an erased cell. The multilevel cell may have multiple Vth windows that each indicate a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell and the stability of the assigned voltage ranges during the lifetime operation of the memory cell.
For example, a cell may be assigned four different voltage ranges of 200 mV for each range. Typically, a dead space or margin of 0.2V to 0.4V is between each range. If the voltage stored on the cell is within the first range, the cell is storing a 00. If the voltage is within the second range, the cell is storing a 01. This continues for as many ranges that are used for the cell provided these voltage ranges remain stable during the lifetime operation of the memory cell.
MLC requires tight control of the threshold voltage ranges and stability of these voltage ranges in order to achieve multiple memory states and associated ranges of threshold levels per cell. For a conventional floating gate or SONOS flash memory cell, the spread in the threshold level (when programmed by a defined set of conditions) of the memory state is affected by several factors. The key factors are: (a) the statistical variations of tunnel oxide thickness and cell coupling coefficient from cell-to-cell; (b) the variation of the trapped charge centroid in density and depth; (c) cell-to-cell variation in trapped charge losses during stand-by (retention), during reading (read disturb), during partial programming (inhibit) and; (d) cell-to-cell variation in endurance (write/erase cycling) characteristics. Additionally, variations in capacitance coupling between adjacent cells creates variation in program disturb differently from cell-to-cell and contribute to the threshold spread.
The above-mentioned factors are critical not only to SLC cell design but considerably more so for the MLC cell design. This is due to the fact that for the flash cell design, the number of well defined logic states to be created within the available programming window (taking all possible Vt spread into consideration) is given by 2n, where n is the number of stored memory bits per cell. For SLC, n=1; for MLC, n=2 (2 bits storage per cell) requires four logic states, and for n=3 (3 bits per cell), eight stable logic states are required within the available programming window. Conventional MLC floating gate and flash memory cells are not voltage scalable since these cells employ SiO2 as the tunneling and charge blocking media which has a dielectric constant of 3.9.
One way to reduce the threshold voltage dispersion is to use a resonant tunnel barrier transistor as illustrated in FIG. 2. Such a transistor is comprised of a normal SiN trapping layer 201, a SiO2 charge blocking layer 202, and a polysilicon gate 203. However, the tunnel dielectric 200 is comprised of a layer of SiO2 210, a layer of amorphous silicon 211, and another layer of SiO2 212. This results in an electron band energy level diagram as illustrated in FIG. 3.
FIG. 3 shows the electron band for the tunnel dielectric 320 that is comprised of the first SiO2 layer 307, the amorphous silicon layer 306, and the second SiO2 layer 305. The electron bands for the SiN trapping layer 304, SiO2 charge blocking layer 303, and gate 301 are also shown.
FIG. 4 illustrates a typical prior art threshold voltage distribution for a conventional SONOS-type structure. Each state, ‘00’ ‘01’ ‘10’ and ‘11’, is shown along the threshold voltage (Vth) axis. This diagram shows that each state has a relatively large threshold window. Such a large window might result in interference from adjacent states as well as limiting the quantity of possible states.
For example, if the ‘11’ state has a peak point of the distribution at 4V, ‘10’ might have a peak point at 3V, ‘01’ might have a peak point at 2V, and ‘00’ might have a peak distribution point of 1V. Each distribution can be +/−0.5V. Additionally, designing such a multi-level memory system requires that each state be separated from the other states by a margin. However, the margin is so small that program disturb conditions may still cause the programming of an undesired state.
FIG. 5 illustrates a typical prior art resonant tunnel barrier threshold voltage distribution. This diagram shows that each threshold voltage distribution has been substantially reduced from the prior art distributions.
The problem with the prior art materials of FIG. 2 is the lack of voltage scalability that they provide. These types of materials still require large voltages for memory cell operation.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for multiple level memory cells to achieve minimal threshold voltage dispersion in programmed states while providing highly scalable cell design.